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ds315 (v1.1) october 31, 2006 www.xilinx.com 1 product specification ? 2004-2006 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as lis ted at http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. features ? aec-q100 device qualification and full ppap support available in both i-grade and extended temperature q-grade ? guaranteed to meet full electrical specifications over t a = -40 c to +105 c with t j maximum = +125 c (q-grade) ? optimized for 1.8v systems - industry?s fastest low power cpld - densities from 32 to 384 macrocells ? industry?s best 0.18 micron cmos cpld - optimized architecture for effective logic synthesis - multi-voltage i/o operation ? 1.5v to 3.3v - guaranteed 1,000 program/erase cycles - guaranteed 20 year data retention ? advanced system features - fastest in system programming 1.8v isp using ieee 1532 (jtag) interface - ieee1149.1 jtag boundary scan test - optional schmitt trigger input (per pin) - multiple i/o banks on all devices - unsurpassed low power management datagate external signal control - flexible clocking modes optional dualedge triggered registers clock divider ( 2,4,6,8,10,12,14,16) coolclock - global signal options with macrocell control multiple global clocks with phase selection per macrocell multiple global output enables global set/reset - abundant product term clocks, output enables and set/resets - efficient control term clocks, output enables and set/resets for each macrocell and shared across function blocks - advanced design security - open-drain output option for wired-or and led drive - optional bus-hold, 3-state or weak pullup on select i/o pins - optional configurable grounds on unused i/os - mixed i/o voltages compatible with 1.5v, 1.8v, 2.5v, and 3.3v logic levels on all parts - hot pluggable ? pla architecture - superior pinout retention - 100% product term routability across function block ? wide package availability including fine pitch: - chip scale bga, tqfp, and vqfp packages - xa devices use pb-free packages ? design entry/verification using xilinx and industry standard cae tools ? free software support for all densities using xilinx webpack? warning: programming temperature range of t a = 0 c to +70 c family overview xilinx coolrunner?-ii automotive cplds deliver the high speed and ease of use associated with the xa9500xl cpld family, along with extremely low power versatility in a single cpld. this means that the exact same parts can be used for high-speed data communications/ computing sys- tems and leading edge portable products, with the added benefit of in system programming. low power consumption and high-speed operation are combined into a single family that is easy to use and cost effective. clocking techniques and other power saving features extend the users? power budget. the design features are supported with xilinx ise webpack. additional details can be found in further reading , page 13 . table 1 shows the macrocell capacity and key timing parameters for the coolrunner-ii automotive cpld family. 0 coolrunner-ii automotive cpld product family ds315 (v1.1) october 31, 2006 00 product specification r table 1: coolrunner-ii automotive cpld family parameters xa2c32a xa2c64a xa2c128 xa2c256 xa2c384 macrocells 32 64 128 256 384 max i/o 33 64 100 118 118 t pd (ns) 5.5 6.7 7.0 7.0 9.2 t su (ns) 2.6 2.5 3.0 2.8 3.3 t co (ns) 4.7 6.0 5.4 6.0 7.9 f system1 (mhz) 200 159 152 152 125
coolrunner-ii automotive cpld product family 2 www.xilinx.com ds315 (v1.1) october 31, 2006 product specification r ta b l e 2 shows the coolrunner-ii automotive cpld pack- age offering with corresponding i/o count. all packages are surface mount, and the ultra tiny packages permit maximum functional capacity in the smallest possible area. the cmos technology used in coolrunner-ii automotive cplds generates minimal heat, allowing the use of tiny packages during high-speed operation. ta b l e 3 details the distribution of advanced features across the coolrunner-ii automotive cpld family. the family has uniform basic features with advanced features included in densities where they are most useful. for example, it is very unlikely that four i/o banks are needed on 32 and 64 mac- rocell parts, but very likely for the 384 macrocell part. the i/o banks are groupings of i/o pins using any one of a sub- set of compatible voltage standards that share the same v ccio level. (see ta b le 4 for a summary of coolrunner-ii automotive cpld i/o standards.) architecture description coolrunner-ii automotive cpld is a highly uniform family of fast, low power cplds. the underlying architecture is a traditional cpld architecture combining macrocells into function blocks (fbs) interconnected with a global routing matrix, the xilinx advanced interconnect matrix (aim). the function blocks use a programmable logic array (pla) configuration which allows all product terms to be routed and shared among any of the macrocells of the fb. design software can efficiently synthesize and optimize logic that is subsequently fit to the fbs and connected with the ability to utilize a very high percentage of device resources. design changes are easily and automatically managed by the soft- ware, which exploits the 100% routability of the program- mable logic array within each fb. this extremely robust building block delivers the industry?s highest pinout reten- tion, under very broad design conditions. the architecture will be explained by expanding the detail as we discuss the underlying function blocks, logic and interconnect. the design software automatically manages these device resources so that users can express their designs using completely generic constructs without knowledge of these architectural details. more advanced users can take advan- tage of these details to more thoroughly understand the software?s choices and direct its results. table 2: coolrunner-ii automotive cpld family packages and i/o count xa2c32a xa2c64a xa2c128 xa2c256 xa2c384 vqg44 33 33 - - - vqg100 - 64 80 80 - cpg132 - - 100 - - TQG144 - - - 118 118 table 3: coolrunner-ii automotive cpld family features xa2c32a xa2c64a xa2c128 xa2c256 xa2c384 ieee 1532 ????? i/o banks 2 2 2 2 4 clock division - - ??? dualedge registers ????? datagate - - ??? lvttl ????? lvcmos33, 25, 18, and 15 (1) ????? configurable ground ????? quadruple data security ????? open drain outputs ????? hot plugging ????? schmitt inputs ????? 1. lvcmos15 requires the use of schmitt-trigger inputs.
coolrunner-ii automotive cpld product family ds315 (v1.1) october 31, 2006 www.xilinx.com 3 product specification r figure 1 shows the high-level architecture whereby func- tion blocks attach to pins and interconnect to each other within the internal interconnect matrix. each fb contains 16 macrocells. the bsc path is the jtag boundary scan con- trol path. the bsc and isp block has the jtag controller and in-system programming circuits. function block the coolrunner-ii automotive cpld function blocks con- tain 16 macrocells, with 40 entry sites for signals to arrive for logic creation and connection. the internal logic engine is a 56 product term pla. all function blocks, regardless of the number contained in the device, are identical. for a high-level view of the function block, see figure 2 . at the high level, it is seen that the product terms (p-terms) reside in a programmable logic array (pla). this structure is extremely flexible, and very robust when compared to fixed or cascaded product term function blocks. classic cplds typically have a few product terms available for a high-speed path to a given macrocell. they rely on capturing unused p-terms from neighboring macrocells to expand their product term tally, when needed. the result of this architecture is a variable timing model and the possibil- ity of stranding unusable logic within the fb. the pla is different ? and better. first, any product term can be attached to any or gate inside the fb macrocell(s). second, any logic function can have as many p-terms as needed attached to it within the fb, to an upper limit of 56. third, product terms can be re-used at multiple macrocell or functions so that within a fb, a particular logical product need only be created once, but can be re-used up to 16 times within the fb. naturally, this plays well with the fitting software, which identifies product terms that can be shared. the software places as many of those functions as it can into fbs, so it happens for free. there is no need to force macrocell functions to be adjacent or any other restriction save residing in the same fb, which is handled by the soft- ware. functions need not share a common clock, common set/reset or common output enable to take full advantage of the pla. also, every product term arrives with the same time delay incurred. there are no cascade time adders for putting more product terms in the fb. when the fb product figure 1: coolrunner-ii automotive cpld architecture function block 1 function block n pla pla i/o blocks i/o blocks 16 16 40 40 16 fb 16 fb 16 16 i/o pin mc1 mc2 mc16 mc1 mc2 mc16 ds090_01_121201 aim i/o pin i/o pin direct inputs bsc and isp clock and control signals bsc path direct inputs i/o pi n i/o pi n i/o pi n jtag figure 2: function block pla 16 40 3 mc1 out to aim global clocks global set/reset mc2 mc16 ds090_02_101001
coolrunner-ii automotive cpld product family 4 www.xilinx.com ds315 (v1.1) october 31, 2006 product specification r term budget is reached, there is a small interconnect timing penalty to route signals to another fb to continue creating logic. xilinx design software handles all this automatically. macrocell the coolrunner-ii automotive cpld macrocell is extremely efficient and streamlined for logic creation. users can develop sum of product (sop) logic expressions that comprise up to 40 inputs and span 56 product terms within a single function block. the macrocell can further combine the sop expression into an xor gate with another single p-term expression. the resulting logic expression?s polarity is also selectable. as well, the logic function can be pure combinatorial or registered, with the storage element oper- ating selectably as a d or t flip-flop, or transparent latch. available at each macrocell are independent selections of global, function block level or local p-term derived clocks, sets, resets, and output enables. each macrocell flip-flop is configurable for either single edge or dualedge clocking, providing either double data rate capability or the ability to distribute a slower clock (thereby saving power). for single edge clocking or latching, either clock polarity may be selected per macrocell. coolrunner-ii macrocell details are shown in figure 3 . note that in figure 3 , standard logic symbols are used except the trapezoidal multiplexers have input selection from statically programmed configuration select lines (not shown). xilinx application note xapp376 gives a detailed explanation of how logic is created in the coolrunner-ii automotive cpld family. when configured as a d-type flip-flop, each macrocell has an optional clock enable signal permitting state hold while a clock runs freely. note that control terms (ct) are available to be shared for key functions within the fb, and are gener- ally used whenever the exact same logic function would be repeatedly created at multiple macrocells. the ct product terms are available for fb clocking (ctc), fb asynchro- nous set (cts), fb asynchronous reset (ctr), and fb out- put enable (cte). any macrocell flip-flop can be configured as an input regis- ter or latch, which takes in the signal from the macrocell?s i/o pin, and directly drives the aim. the macrocell combina- tional functionality is retained for use as a buried logic node if needed. f toggle is the maximum clock frequency to which a t flip-flop can reliably toggle. figure 3: coolrunner-ii cpld macrocell gck0 gck1 gck2 ctc ptc ptc ds090_03_121201 49 p-terms to pta, ptb, ptc of other macrocells ctc, ctr, cts, cte from aim 4 p-terms pta direct input from i/o block feedback to aim ptb ptc pla or term pta cts gsr gnd gnd v cc r d/t ce ck fif latch dualedge q s 40 to i/o block pta ctr gsr gnd
coolrunner-ii automotive cpld product family ds315 (v1.1) october 31, 2006 www.xilinx.com 5 product specification r advanced interconnect matrix (aim) the advanced interconnect matrix is a highly connected low power rapid switch. the aim is directed by the software to deliver up to a set of 40 signals to each fb for the cre- ation of logic. results from all fb macrocells, as well as, all pin inputs circulate back through the aim for additional con- nection available to all other fbs as dictated by the design software. the aim minimizes both propagation delay and power as it makes attachments to the various fbs. i/o block i/o blocks are primarily transceivers. however, each i/o is either automatically compliant with standard voltage ranges or can be programmed to become so. see xapp382 for detailed information on coolrunner-ii i/os. in addition to voltage levels, each input can selectively arrive through schmitt-trigger inputs. this adds a small time delay, but substantially reduces noise on that input pin. approximately 500 mv of hysteresis will be added when schmitt-trigger inputs are selected. all lvcmos inputs can have hysteresis input. hysteresis also allows easy genera- tion of external clock circuits. the schmitt-trigger path is best seen in figure 4 . see ta b le 4 for schmitt-trigger com- patibility with i/o standards. outputs can be directly driven, 3-stated or open-drain con- figured. a choice of slow or fast slew rate output signal is also available. ta b l e 4 summarizes various supported volt- age standards associated with specific part capacities. all inputs and disabled outputs are voltage tolerant up to v ccio . ta b l e 4 summarizes the single ended i/o standard support. output banking cplds are widely used as voltage interface translators. to that end, the output pins are grouped in large banks. the 32, 64,128, and 256-macrocell devices support two output banks. each bank can be set to a selected output voltage level. if you want only one output voltage level, both banks can be set to the same voltage. the large part (384-macro- cell) supports four output banks split evenly. it can support groupings of one, two, three or four separate output voltage levels. this kind of flexibility permits easy interfacing to 3.3v, 2.5v, 1.8v, and 1.5v in a single part. datagate low power is the hallmark of cmos technology. other cpld families use a sense amplifier approach to creating product terms, which always has a residual current compo- nent being drawn. this residual current can be several hun- dred milliamps, making them unusable in portable systems. coolrunner-ii automotive cplds use standard cmos methods to create the cpld architecture and deliver the corresponding low current consumption, without doing any special tricks. however, sometimes designers would like to figure 4: coolrunner-ii automotive cpld i/o block diagram enabled to macrocell direct input to aim 4 cte ptb gts[0:3] cgnd open drain from macrocell v ccio disabled hysteresis global termination pullup/bus-hold ds315_04_091906 table 4: coolrunner-ii automotive cpld i/o standard summary iostandard attribute v ccio schmitt-trigger support lvttl 3.3 optional lvcmos33 3.3 optional lvcmos25 2.5 optional lvcmos18 1.8 optional lvcmos15 1.5 required
coolrunner-ii automotive cpld product family 6 www.xilinx.com ds315 (v1.1) october 31, 2006 product specification r reduce their system current even more by selectively dis- abling circuitry not being used. the patented datagate technology was developed to per- mit a straightforward approach to additional power reduc- tion. each i/o pin has a series switch that can block the arrival of free running signals that are not of interest. sig- nals that serve no use may increase power consumption, and can be disabled. users are free to do their design, then choose sections to participate in the datagate function. datagate is a logic function that drives an assertion rail threaded through the medium and high-density coolrun- ner-ii automotive cpld parts. designers can select inputs to be blocked under the control of the datagate function, effectively blocking controlled switching signals so they do not drive internal chip capacitances. output signals that do not switch, are held by the bus hold feature. any set of input pins can be chosen to participate in the datagate function. figure 5 shows how datagate basically works. one i/o pin drives the datagate assertion rail. it can have any desired logic function on it. it can be as simple as mapping an input pin to the datagate function or as complex as a counter or state machine output driving the datagate i/o pin through a macrocell. when the datagate rail is asserted high, any pass transistor switch attached to it is blocked. note that each pin has the ability to attach to the aim through a datagate pass transistor, and thus be blocked. a latch automatically captures the state of the pin when it becomes blocked. the datagate assertion rail threads throughout all possible i/os, so each can participate if chosen. note that one macrocell is singled out to drive the rail, and that macrocell is exposed to the outside world through a pin, for inspection. if datagate is not needed, this pin is an ordinary i/o. global signals global signals, clocks (gck), sets/resets (gsr) and output enables (gts), are designed to strongly resemble each other. this approach enables design software to make the best utilization of their capabilities. each global capability is supplemented by a corresponding product term version. figure 6 shows the common structure of the global signal trees. the pin input is buffered, then drives multiple internal global signal traces to deliver low skew and reduce loading delays. gck, gsr, and gts can also be used as general figure 5: datagate architecture (output drivers not shown) pla mc1 mc2 mc16 ds090_06_111201 pla pla datagate assertion rail pla aim mc1 mc2 mc16 mc1 mc2 mc16 mc1 mc2 mc16 to aim latch to aim latch to aim to aim latch latch to aim latch
coolrunner-ii automotive cpld product family ds315 (v1.1) october 31, 2006 www.xilinx.com 7 product specification r purpose i/o if they are not needed as global signals. the datagate assertion rail is also a global signal. additional clock op tions: division, dualedge, and coolclock division circuitry has been included in the coolrunner-ii automo- tive cpld architecture to divide one externally supplied glo- bal clock by standard values. division by 2,4,6,8,10, 12, 14 and 16 are the options (see figure 7 ). this capability is sup- plied on the gck2 pin. the resulting clock produced will be 50% duty cycle for all possible divisions. note that a syn- chronous reset (cdrst) is included to guarantee no runt clocks can get through to the global clock nets. note that again, the signal is buffered and driven to multiple traces with minimal loading and skew. dualedge each macrocell has the ability to double its input clock switching frequency. figure 8 shows the macrocell flip-flop with the dualedge option (doubled clock) at each macro- cell. the source to double can be a control term clock, a product term clock or one of the available global clocks. the ability to switch on both clock edges is vital for a number of synchronous memory interface applications as well as cer- tain double data rate i/o applications. coolclock in addition to the dualedge flip-flop, additional power sav- ings can be had by combining the clock division circuitry with the dualedge circuitry. this capability is called cool- clock and is designed to reduce clocking power within the cpld. because the clock net can be an appreciable power drain, the clock power can be reduced by driving the net at half frequency, then doubling the clock rate using dualedge triggering at the macrocells. figure 9 shows how coolclock is created by internal clock cascading with the divider and dualedge flip-flop working together. see xapp378 for more detail. figure 6: global clocks (gck), sets/resets (gsr) and output enables (gts) ds090_07_101001 figure 7: clock division circuitry for gck2 ds090_08_121201 clock in 2 4 6 8 10 12 14 16 gck2 cdrst cdrst
coolrunner-ii automotive cpld product family 8 www.xilinx.com ds315 (v1.1) october 31, 2006 product specification r design security designs can be secured during programming to prevent either accidental overwriting or pattern theft via readback. four independent levels of security are provided on-chip, eliminating any electrical or visual detection of configuration patterns. these security bits can be reset only by erasing the entire device. see wp170 for more detail. figure 8: macrocell clock chain with dualedge option shown figure 9: coolclock created by cascading cl ock divider and dualedge option gck0 gck1 gck2 clk_ct ptc ptc ds090_09_121201 d/t ce ck fif latch dualedge q ? gck0 gck1 gck2 ctc ptc ptc d/t ce ck fif latch dualedge q clock in w 2 w 4 w 6 w 8 w 10 w 12 w 14 w 16 gck2 cdrst cdrst
coolrunner-ii automotive cpld product family ds315 (v1.1) october 31, 2006 www.xilinx.com 9 product specification r timing model figure 10 shows the coolrunner-ii cpld timing model. it represents one aspect of the overall architecture from a tim- ing viewpoint. each little block is a time delay that a signal will incur if the signal passes through such a resource. tim- ing reports are created by tallying the incremental signal delays as signals progress within the cpld. software cre- ates the timing reports after a design has been mapped onto the specific part, and knows the specific delay values for a given speed grade. equations for the higher level tim- ing values (i.e., t pd and f system ) are available. ta b le 5 summarizes the individual parameters and provides a brief definition of their associated functions. xilinx application note xapp375 details the coolrunner-ii automotive cpld family timing with several examples. figure 10: coolrunner-ii automotive cpld timing model note: always refer to the timing report in ise software for accurate timing values for paths. d/t s/r t f t sui t hi t coi t aoi t ecsu t echo t out t slew t en xapp375_03_010303 t oem t pdi t logi2 t logi1 t in t hys ce t din t hys t ct t gck t hys t gsr t hys t gts t hys table 5: timing parameter definitions symbol parameter buffer delays t ln input buffer delay t din direct data register input delay t gck global clock (gck) buffer delay t gsr global set/reset (gsr) buffer delay t gts global output enable (gts) buffer delay t out output buffer delay t en output buffer enable/disable delay t slew output buffer slew rate control delay p-term delays t ct control term delay (single pt or fb-ct) t logi1 single p-term logic delay t logi2 multiple p-term logic delay adder macrocell delays t pdi macro cell input to output valid t sui macro register setup before clock t hi macro register hold after clock t ecsu macro register enable clock setup time t echo macro register enable clock hold time t coi macro register clock to output valid t aoi macro register set/reset to output valid t hys hysteresis selection delay adder feedback delays t f feedback delay t oem macrocell to global oe delay table 5: timing parameter definitions (continued) symbol parameter
coolrunner-ii automotive cpld product family 10 www.xilinx.com ds315 (v1.1) october 31, 2006 product specification r programming the programming data sequence is delivered to the device using either xilinx impact software and a xilinx download cable, a third-party jtag development system, a jtag-compatible board tester, or a simple microprocessor interface that emulates the jtag instruction sequence. the impact software also outputs serial vector format (svf) files for use with any tools that accept svf format, including automatic test equipment. coolrunner-ii automotive cpld devices must be programmed at temperatures of t a = 0 c to +70 c only.see coolrunner-ii application notes for more information on how to program. in system programming all coolrunner-ii automotive cpld parts are 1.8v in sys- tem programmable. this means they derive their program- ming voltage and currents from the 1.8v v cc (internal supply voltage) pins on the part. the v ccio pins do not par- ticipate in this operation, as they may assume another volt- age ranging as high as 3.3v down to 1.5v. a 1.8v v cc is required to properly operate the internal state machines and charge pumps that reside within the cpld to do the nonvol- atile programming operations. the jtag interface buffers are powered by a dedicated power pin, v ccaux , which is independent of all other supply pins. v ccaux must be con- nected. xilinx software is provided to deliver the bit-stream to the cpld and drive the appropriate ieee 1532 protocol. to that end, there is a set of ieee 1532 commands that are supported in the coolrunner-ii automotive cpld parts. programming times are less than one second for 32 to 256 macrocell parts. programming times are less than four sec- onds for 384 macrocell part. programming of coolrunner-ii automotive cplds is only guaranteed when operating in the commercial temperature and voltage ranges as defined in the device-specific data sheets. jtag instructions ta b l e 6 shows the commands available to users. these same commands may be used by third party ate products, as well. the internal controllers can operate as fast as 66 mhz. power-up characteristics coolrunner-ii automotive cpld parts must operate under the demands of both the high-speed and the portable mar- ket places, therefore, they must support hot plugging for the high-speed world and tolerate most any power sequence to its various voltage pins. they must also not draw excessive current during power-up initialization. to those ends, the general behavior is summarized as follows: 1. i/o pins are disabled until the end of power-up. 2. as supply rises, configuration bits transfer from nonvolatile memory to sram cells. 3. as power up completes, the i/os become configured. 4. for specific configuration times and power up requirements, see the device specific data sheet. coolrunner-ii automotive cpld i/o pins are well behaved under all operating conditions. during power-up, coolrun- ner-ii devices employ internal circuitry which keeps the devices in the quiescent state until the v ccint supply volt- age is at a safe level (approximately 1.3v). in the quiescent state, jtag pins are disabled, and all device outputs are disabled with the pins weakly pulled high, as shown in table 8 . when the supply voltage reaches a safe level, all user registers become initialized, and the device is immediately available for operation, as shown in figure 12 (best results are obtained with a monotonic v cc rise in less than 1 ms). if the device is in the erased state (before any user pattern is programmed), the device outputs remain disabled with a weak pull-up. the jtag pins are enabled to allow the device to be programmed at any time. all devices are shipped in the erased state from the factory. applying power to a blank part may result in a higher current flow as the part initializes. this behavior is normal and may persist for approximately 2 seconds, depending on the power supply ramp. if the device is programmed, the device inputs and outputs take on their configured states for normal operation. the jtag pins are enabled to allow device erasure or bound- ary-scan tests at any time. table 6: jtag instructions code instruction description 00000000 extest force boundary scan data onto outputs 00000011 preload latch macrocell data into boundary scan cells 11111111 bypass insert bypass register between tdi and tdo 00000010 intest force boundary scan data onto inputs and feedbacks 00000001 idcode read idcode 11111101 usercode read usercode 11111100 highz force output into high impedance state 11111010 clamp latch present output state table 6: jtag instructions code instruction description
coolrunner-ii automotive cpld product family ds315 (v1.1) october 31, 2006 www.xilinx.com 11 product specification r i/o banking two v ccio rails are supported on the coolrunner-ii auto- motive cpld 32, 64, 128 and 256 macrocell parts where outputs on each rail can independently range from 3.3v down to 1.5v operation. four v ccio rails are supported on the 384 macrocell part. any of the v ccio rails can assume any one of the v ccio values of 1.5v, 1.8v, 2.5v, or 3.3v. designers should assign input and output voltages to a bank with v ccio set at the voltage range of that input or out- put voltage. the v cc (internal supply voltage) for a cool- runner-ii automotive cpld must be maintained within 1.8v 5% for correct speed operation and proper in system programming. mixed voltage, power sequencing, and hot plugging as mentioned in i/o banking, coolrunner-ii automotive cpld parts support mixed voltage i/o signals. it is impor- tant to assign signals to an i/o bank with the appropriate i/o voltage. driving a high voltage into a low voltage bank can result in negative current flow through the power supply pins. the power applied to the v ccio and v cc pins can occur in any order and the coolrunner-ii automotive cpld will not be damaged. for best results, we recommend that v ccint be applied before v ccio . this will ensure that the internal logic is correct before the i/os are active. coolrun- ner-ii automotive cplds can reside on boards where the board is inserted into a ?live? connector (hot plugged) and the parts will be well-behaved as if powering up in a stan- dard way. development system support xilinx coolrunner-ii automotive cplds are supported by all configurations of xilinx standard release development software as well as the freely available ise webpack soft- ware available from www.xilinx.com . third party develop- ment tools include synthesis tools from cadence, exemplar, mentor graphics, synplicity, and synopsys. ate support third party ate development support is available for both programming and board/chip level testing. vendors provid- ing this support include agilent, genrad, and teradyne. other third party providers are expected to deliver solutions in the future. figure 11: device behavior during power up v ccint no power 3.8 v (typ) 0v no powe r quiescent state quiescent state user operation initialization transition of user array x382_10 1.3v (typ) table 7: i/o power-up characteristics device circuitry quiescent state erased device operation valid user operation iob bus-hold/weak pullup weak pull-up weak pull-up bus-hold/weak pullup device outputs disabled disabled as configured device inputs and clocks disabled disabled as configured function block disabled disabled as configured jtag controller disabled enabled enabled
coolrunner-ii automotive cpld product family 12 www.xilinx.com ds315 (v1.1) october 31, 2006 product specification r absolute maximum ratings (1) coolrunner-ii automotive data sheets http://direct.xilinx.com/bv docs/publications/ds552.pdf (xa2c32a datasheet) http://direct.xilinx.com/bv docs/publications/ds553.pdf (xa2c64a datasheet) http://direct.xilinx.com/bv docs/publications/ds554.pdf (xa2c128 datasheet) http://direct.xilinx.com/bv docs/publications/ds555.pdf (xa2c256 datasheet) http://direct.xilinx.com/bv docs/publications/ds556.pdf (xa2c384 datasheet) quality and reliability parameters coolrunner-ii automotive requirements and recommendations requirements the following requirements are for all automotive applica- tions: 1. use a monotonic, fast ramp power supply to power up coolrunner-ii . a v cc ramp time of less than 1 ms is required. 2. do not float i/o pins during device operation. floating i/o pins can increase i cc as input buffers will draw 1-2 ma per floating input. in addition, when i/o pins are floated, noise can propagate to the center of the cpld. i/o pins should be appropriately terminated with bus-hold or pull-up. unused i/os can also be configured as c gnd (programmable gnd). 3. do not drive i/o pins without v cc /v ccio powered. 4. sink current when driving leds. because all xilinx cplds have n-channel pull-down transistors on outputs, it is required that an led anode is sourced through a resistor externally to v cc . consequently, this will give the brightest solution. 5. avoid pull-down resistors. always use external pull-up resistors if external termination is required. this is because the coolrunner-ii automotive cpld, which includes some i/o driving circuits beyond the input and output buffers, may have contention with external pull-down resistors, and, consequently, the i/o will not switch as expected. 6. do not drive i/os pins above the v ccio assigned to its i/o bank. a. the current flow can go into v ccio and affect a user voltage regulator. b. it can also increase undesired leakage current associated with the device. c. if done for too long, it can reduce the life of the device. symbol parameter min. max. unit v cc (2) supply voltage relative to gnd ?0.5 2.0 v v i (3) input voltage relative to gnd ?0.5 4.0 v t j (4) maximum junction temperature ?40 125 c t str storage temperature (ambient) ?65 150 c notes: 1. stresses above those listed may cause malfunction or permanent damage to the device. this is a stress rating only. functional operation at these or any other condition above those indicated in the operational and programming specification is not implied . 2. the chip supply voltage should rise monotonically. 3. maximum dc undershoot below gnd must be limited to either 0.5v or 10 ma, whichever is easier to achieve. during transitions, the device pins may undershoot to ?2.0v or overshoot to 4.5 v, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 ma. the i/o voltage may never exceed 4.0v. 4. for soldering guidelines and thermal considerations, see the device packaging information on the xilinx website. for pb-free packages, see xapp427 . symbol parameter min max units t dr data retention 20 - years n pe program/erase cycles (endurance) 1,000 - cycles
coolrunner-ii automotive cpld product family ds315 (v1.1) october 31, 2006 www.xilinx.com 13 product specification r 7. do not rely on the i/o states before the cpld configures. 8. use a voltage regulator which can provide sufficient current during device power up. as a rule of thumb, the regulator needs to provide at least three times the peak current while powering up a cpld in order to guarantee the cpld can configure successfully. 9. ensure external jtag terminations for tms, tck, tdi, tdo comply with ieee 1149.1. all xilinx cplds have internal weak pull-ups of ~50 k on tdi, tms, and tck. 10. attach all cpld v cc and gnd pins in order to have necessary power and ground supplies around the cpld. 11. decouple all v cc and v ccio pins with capacitors of 0.01 f and 0.1 f closest to the pins for each v cc /v ccio -gnd pair. 12. configure i/os properly. coolrunner-ii automotive cplds have i/o banks; therefore, signals must be assigned to appropriate banks (lvcmos33, lvcmos18 ?) recommendations the following recommendations are for all automotive appli- cations. 1. use strict synchronous design (only one clocking event) if possible. a synchronous system is more robust than an asynchronous one. 2. include jtag stakes on the pcb. jtag stakes can be used to test the part on the pcb. they add benefit in reprogramming part on the pcb, inspecting chip internals with intest, identifying stuck pins, and inspecting programming patterns (if not secured). 3. coolrunner-ii automotive cplds work with any power sequence, but it is preferable to power the v cci (internal v cc ) before the v ccio for the applications in which any glitches from device i/os are unwanted. 4. do not disregard report file warnings. software identifies potential problems when compiling, so the report file is worth inspecting to see exactly how your design is mapped onto the logic. 5. understand the timing report. this report file provides a speed summary along with warnings. read the timing file (*.tim) carefully. analyze key signal chains to determine limits to given clock(s) based on logic analysis. 6. review fitter report equations. equations can be shown in abel-like format, or can also be displayed in verilog or vhdl formats. the fitter report also includes switch settings that are very informative of other device behaviors. 7. let design software define pinouts if possible. xilinx cpld software works best when it selects the i/o pins and manages resources for users. it can spread signals around and improve pin-locking. if users must define pins, plan resources in advance. 8. perform a post-fit simulation for all speeds to identify any possible problems (such as race conditions) that might occur when fast-speed silicon is used instead of slow-speed silicon. 9. distribute ssos (simultaneously switching outputs) evenly around the cpld to reduce switching noise. 10. terminate high speed outputs to eliminate noise caused by very fast rising/falling edges. automotive warranty disclaimer this warranty does not extend to any implementation in an application or environment that is not contained within xilinx specifications. pro ducts are not designed to be fail-safe and are not warranted for use in the deployment of ai rbags. further, products are not warranted for use in applications that affect control of the vehicle unless there is a fail-safe or redundancy feature and also a warning signal to the operator of the vehicle upon failure. use of products in such applications is fully at the risk of customer subject to applicable laws and regulations governing limitations on product liability. further reading application notes http://direct.xilinx.com/bvdocs/appnotes/xapp784.pdf (bulletproof design practices) http://direct.xilinx.com/bvdocs/appnotes/xapp375.pdf (timing model) http://direct.xilinx.com/bvdocs/appnotes/xapp376.pdf (logic engine) http://direct.xilinx.com/bvdocs/appnotes/xapp377.pdf (low power design) http://direct.xilinx.com/bv docs/appnotes/xapp378.pd f (advanced features) http://direct.xilinx.com/bvdocs/appnotes/xapp379.pdf (high speed design ) http://direct.xilinx.com/bvdocs/appnotes/xapp380.pdf (cross point switch)
coolrunner-ii automotive cpld product family 14 www.xilinx.com ds315 (v1.1) october 31, 2006 product specification r http://direct.xilinx.com/bvdocs/appnotes/xapp381.pdf (demo board) http://direct.xilinx.com/bvdocs/appnotes/xapp382.pdf (i/o characteristics) http://direct.xilinx.com/bvdocs/appnotes/xapp383.pdf (single error correction double error detection) http://direct.xilinx.com/bvdocs/appnotes/xapp384.pdf (ddr sdram interface) http://direct.xilinx.com/bvdocs/appnotes/xapp387.pdf (picoblaze microcontroller) http://direct.xilinx.com/bvdocs/appnotes/xapp388.pdf (on the fly reconfiguration) http://direct.xilinx.com/bvdocs/appnotes/xapp389.pdf (powering coolrunner-ii) http://direct.xilinx.com/bvdocs/appnotes/xapp393.pdf (8051 microcontroller interface) http://direct.xilinx.com/bvdocs/appnotes/xapp394.pdf (interfacing with mobile sdram) http://direct.xilinx.com/bvdocs/appnotes/xapp399.pdf (assigning coolrunner-ii vref pins) coolrunner-ii white papers http://direct.xilinx.com/bvdocs/whitepapers/wp170.pdf (security) revision history the following table shows the revision history for this document. date version revision 10/18/04 1.0 initial xilinx release 10/31/06 1.1 re-released with individual data sheets for xa2c32a, xa2c64a, xa2c128, xa2c256, and xa2c384

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